1. Field of the Invention
Embodiments of the present invention generally relate to cache memories. More specifically, embodiments of the present invention relate to techniques for using non-address information to generate indices to access entries in a cache memory.
2. Related Art
Nearly all computer systems include a memory structure which stores a number of entries that is smaller than a set of items that the memory structure is designed to store. For example, many computer systems include a cache memory that provides fast local storage for a small amount of data from a slower main memory. Caches typically store far fewer entries than the number of memory locations in the main memory. Consequently, each entry in a cache must be available for storing data from a number of different locations in main memory. Translation lookaside buffers (TLBs) are another example of such a memory structure.
In order to store data items in these memory structures, some systems generate indices for the data items and then use the generated indices to determine an entry in the memory structure where data item should be located. For example, during a cache access, the address of the cache line is used to generate an index which the system uses to determine an entry in the cache where the cache line should be located. Similarly, for a TLB lookup operation, a virtual address is used to generate an index in the TLB where a corresponding physical address should be stored.
Unfortunately, using addresses to generate indices can lead to unbalanced utilization of entries in these types of memory structures. For example, more than one thread may be accessing the same range of addresses in a cache and will consequently be generating the same indices. The repeated generation of the same indices can lead to a large number of accesses to the same locations in the cache, which can cause the threads to interfere with each other and thereby adversely affect performance.
Hence, what is needed is a cache memory without the above-described problem.